The fabrication of integrated circuit (IC) chips has become a sophisticated process that can allow complex circuitry to be densely packaged onto a single substrate or wafer. Originally, most chips were fabricated in a simple planar design. However, planar chip designs limit the amount of circuitry that can be placed on a single substrate.
To overcome some of the limitations resulting from the planar design, designers began stacking chips to form three-dimensional designs. Vias extending through the substrate—i.e., “through-substrate vias”—create three-dimensional interconnects which facilitate connection to the circuitry throughout the chip, thereby allowing the implementation of more advanced circuits and enabling a higher density of complex circuitry to be placed within a given die area. Furthermore, a three-dimensional design with through-substrate vias can enable advanced micro-electronic chip stacking, which can result, for example, in increased processing power for image data and signal processing.
Although three-dimensional chips using through-substrate vias have proven useful, they are currently limited. In one approach, through-substrate vias have been formed in thick substrates—e.g., 200-400 μm; the thickness enables the substrates to retain mechanical durability and to be easily handled and processed without the need for sequential stacking and thinning operations. Using this approach, substrates are etched and the formed vias are electrically insulated and metallized.
Although this approach provides some advantages, it introduces other limitations, such as the inability to fabricate small-diameter, fine-pitch vias. Indeed, using current etching techniques, the formation of high aspect ratio (i.e., ratio of depth to diameter) vias results in a large diameter-to-pitch (i.e., the center-to-center measurement between vias) ratio for the vias. This limits the etch depth of the vias, and also reduces the amount of available space on the substrate for other uses. Current techniques typically produce vias having diameters of about 4 μm with a depth of about 20 μm (using low temperature techniques) and 100 μm diameters with a depth of about 500 μm (using high temperature techniques); thus, an aspect ratio of about 5:1 is provided with either high or low temperature techniques. Both dry etching and wet etching have been demonstrated for the thick wafer processing, and both suffer from constraints on via size and separation. In addition, it is very difficult to reliably deposit electrical isolation layers and metallic conductors using low process temperatures in high aspect ratio vias.
To reduce via diameters, some techniques sequentially stack, bond and thin multiple wafers into a ‘single’ wafer stack and form the vias through only a single thin layer of the stacked wafers at a time, thereby reducing the aspect ratio and diameter required of an individual via. This approach involves wafer ‘thinning’, in which the wafers to be stacked are bonded and one portion (non-circuit containing, exposed surface) of the stacked wafers is thinned to reduce the wafer thickness, typically down to 10-25 μm. At this thickness, small diameter vias can be etched through the thinned layer while maintaining separation between neighboring vias. Alternatively, the via could be etched to a limited depth prior to the bonding, and then have its bottom (non-circuit containing) surface exposed in the thinning operation after bonding.
This approach can use well-developed fabrication processes; however, disadvantages arise from the need for sequential processing of each successive layer and the complexity of intermediate testing. Further, the thinning of the stacked wafers reduces their integrity and makes them more susceptible to breakage during use and damage from handling. Further still, many current bonding techniques involve high temperatures, high voltage and/or high pressure, each of which poses difficulties if the stacking includes prefabricated integrated circuits with multi-level interconnects. Further, in this approach sequential circuit wafers can only be stacked in one orientation, with active circuitry at the bond interface, since the thinning process must only remove unprocessed substrate. Finally, the wafer-level sequential stacking can introduce stacked device yield impacts resulting from the random alignment of defects in a die from one layer with a good die in another, reducing operability at the stack level.
In addition to a hole that passes completely through a substrate, a through-substrate via generally also requires an insulating layer lining the inner surfaces of the hole, and a conductive layer over the insulating layer. For a high aspect ratio via having a narrow diameter, it can be difficult to provide these insulating and conductive layers. One technique for forming such a via is described in co-pending patent application Ser. No. 11/167,014 to Borwick et al. and assigned to the present assignee. Here, wet processing is used to provide the via's sidewall seed layer and conductive layer. However, it can be difficult to achieve uniform seed layer coverage using wet processing, and particulates in the liquid solution can clog the vias, particularly those having a small diameter.
Another problem that can occur when fabricating through-substrate vias is the failure to completely fill one or more of the vias, such that continuous top-to-bottom openings through the via are present.